1. Field of the invention
The present invention relates to a semiconductor device manufacturing method, and more specifically a method for forming a cylindrical capacitor lower plate in a semiconductor device.
2. Description of Related Art
Of semiconductor memories, a DRAM (dynamic random access memory) is known as a memory possible to freely write and read information. In this DRAM memory, the simplest memory cell consists of one transfer transistor and one capacitor (one transistor type memory cell), and is widely used since it is the most suitable for increasing an integration density of the semiconductor device.
For a capacitor incorporated in this type of memory cell, a three-dimensional structure has been developed and actually used in order to further elevate the integration density of the semiconductor device. The reason for adopting the three-dimensional structure of capacitor, is that, with advanced microminiaturization and elevated integration density of semiconductor device elements, an occupying area of the capacitor is inevitably reduced, but on the other hand, a capacitance not less than a predetermined value is required to ensure a stable and reliable operation of the DRAM. Under this circumstance, by replacing a planar structure of capacitor plates by a three-dimensional structure of capacitor plates, it was attempted to increase an effective area of the of capacitor plates under a reduced occupying area of the capacitor.
The three-dimensional capacitor for the DRAM includes a stacked structure and a trench structure, which have both merits and demerits. The stacked structure is highly resistive to an alpha ray incidence and noises from other circuits, and stably operates with a relatively small capacitance. Therefore, even in a 1-Gbit DRAM manufactured on 0.15 .mu.m rule in the semiconductor device design, the stacked structure capacitor is considered to be effective. However, in a simple stacked capacitor structure, it is predicted that a height of a capacitor plate is required to be larger than about 0.8 .mu.m in a 256 Mbit DRAM and about 1.2 .mu.m in a 1 Gbit DRAM. But, this is not practical, since there exists a strong demand for suppressing the height of the capacitor plate because a wiring disconnection is apt to occur due to a large step difference and because a depth of field is limited in a photolithography.
Under the above mentioned circumstances, as one kind of the stacked structure capacitor, attention is attracted to a structure called a "cylinder type". For example, Japanese Patent Application Laid-open Publication Nos. JP-A-5-136371 and JP-A-6-029463 have proposed to form a capacitor lower plate in the form of a cylinder, for the purpose of increasing a surface area of the capacitor plate.
Now, a prior art process for forming a lower plate of the cylinder type stacked structure capacitor will be described with reference to FIGS. 1A to 1F, which are diagrammatic sectional views for illustrating the prior art process for forming a lower plate of the cylinder type stacked structure capacitor.
As shown in FIG. 1A, a field oxide film 2 is formed as a device isolation insulating film on a silicon substrate 1 of for example P-type. For each memory cell transistor, a gate electrode 3 (functioning as a word line) of each memory cell transistor is formed through a gate insulator film on a principal surface of the substrate 1, and a pair of N.sup.+ source/drain diffused regions 4 and 5 are formed in a principal surface region of the substrate 1. The diffused region 4 is to be connected to a possible capacitor, and the diffused region 5 is to be connected to a bit line. A silicon oxide film is deposited to form an interlayer insulator film 6A covering the gate electrode (word line) 3 and the principal surface of the substrate 1, and a bit line contact plug 9 is formed to penetrate through the interlayer insulator film 6A to reach the diffused region 5 for the bit line. A bit line 8 is formed on the interlayer insulator film 6A and to be electrically connected to the bit line contact plug 9. Furthermore, an interlayer insulator film 6B is also deposited to cover the bit line 8 and the interlayer insulator film 6A.
Thereafter, a stopper film 7 is deposited to cover the interlayer insulator film 6B. This stopper film 7 is formed of for example a silicon nitride film.
Then, a contact hole 10 is formed to penetrate through the stopper film 7 and the interlayer insulator films 6A and 6B to reach the diffused region 4 for the possible capacitor, and a first silicon film 11 is deposited by a known CVD (chemical vapor deposition) process to fill the contact hole 10 and to cover the stopper film 7. This first silicon film 11 forms a portion of a storage plate (lower plate) of the possible capacitor. Furthermore, a spacer film 12 is formed to cover the first silicon film 11. This spacer film 12 is formed of for example a silicon oxide form deposited by a known CVD process. The reason for this is that, in a step for removing the spacer film 12, which will be conducted in a later stage, a substantial selective etching ratio is ensured between the spacer film 12 and the stopper film 7.
Thereafter, a patterned photoresist film 13 having a desired pattern is formed by depositing, exposing and developing a photoresist by use of a known photolithography.
Then, an anisotropic dry etching is conducted by a known RIE (reactive ion etching) process, and by using the patterned photoresist film 13 as a mask, so that the spacer film 12 and the first silicon film 11 are patterned together, as shown in FIG. 1B. For example, this anisotropic dry etching is conducted as follows: First, the spacer film 12 formed of silicon oxide is etched by using a mixed gas containing CF4 gas and CHF3 gas as main components, and succeedingly, the first silicon film 11 is etched by using a mixed gas containing Cl2 gas and HBr gas as main components. In the course of etching the spacer film 12, a deposit 14 formed of a fluorocarbon polymer is deposited on a sidewall of the patterned spacer film 12, with progress of the etching and simultaneously as the sidewall itself is formed by the etching. This sidewall deposit 14 prevents advance of a sidewall etching of the patterned spacer film 12, with the result that the anisotropic etching becomes possible. This sidewall deposit 14 has a thickness on the order of 10 nm to 20 nm. Since the silicon film 11 is etched by using the mask including the thickness of the deposit 14, a patterned silicon film 11A becomes different in size from a patterned spacer film 12A.
Next, as shown in FIG. 1C, the photoresist film 13 is removed. In the process for removing the photoresist film 13, however, not only the photoresist film 13 and the deposit 14 are removed, but also the patterned silicon film 11A and the patterned spacer film 12A are etched with a thickness of 1 nm to 2 nm and a thickness of 10 nm to 30 nm, respectively, with the result that an enlarged difference in size occurs between a patterned silicon film 11B and a patterned spacer 12B.
Then, as shown in FIG. 1D, a second silicon film 15 is deposited to cover the whole surface by the CVD process.
Furthermore, as shown in FIG. 1E, an anisotropic dry etching is conducted by a known RIE process, so that a sidewall 15A of the second silicon film is left to cover a side surface of the patterned spacer 12B and the patterned silicon film 11B. For example, this anisotropic dry etching is conducted by using a mixed gas containing Cl2 and HBr as main components.
Thereafter, as shown in FIG. 1F, the patterned spacer 12B is selectively removed by a hydrogen fluoride aqueous solution. Then, impurity such as arsenic or phosphorus is introduced into the patterned first silicon film 11B and the patterned second silicon film 15B in order to elevate conductivity of these films. Thus, a capacitor information storage plate (formed of a lower plate composed of a base 11B and a sidewall 15B) is finished. Thereafter, a dielectric film (not shown) is deposited, and an opposing plate (also not shown) is formed, so that the capacitor is completed.
In the above mentioned prior art process, however, since the first silicon film 11 is patterned after the spacer film 12A is patterned but before the photoresist film 13 and the deposit 14 are removed, the difference in size occurs between the spacer film 12A and the first silicon film 11A as shown in FIG. 1B, and then, in the step for removing the photoresist film 13, the difference in size between the spacer film 12B and the first silicon film 11B becomes large.
If this difference in size, designated by Reference Sign "b" in FIG. 1F, is large, a mechanical strength in a portion enclosed by a circle "A" in FIG. 1F becomes insufficient, so that the portion "A" is broken or destroyed in a washing step, with the result that a yield of production also drops.
In order to avoid the above mentioned problem, if a film thickness "c" of the second silicon film 15 is increased, a distance "d" between adjacent information storage plates becomes small, so that a short-circuit becomes easy to occur in a portion "B" in FIG. 1F. In this case, a yield of production drops.
Accordingly, it may be considered to increase the film thickness "c" of the second silicon film 15 and also to increase the distance "d" between adjacent information storage plates. However, from a viewpoint of design, a pitch "a+e" of the information storage plates is required to be maintained at a constant value. In addition, since there is a relation of a=2c+d in FIG. 1F, it is necessary to reduce "e" in order to increase the film thickness "c" and the distance "d" while maintaining the pitch "a+e" at the constant value. Here, "e" is a diameter of the patterned first silicon film 11B, and "a" is a distance or spacing between adjacent patterned first silicon films 11B. If the diameter "e" is reduced, the information storage plate becomes small as a whole, so that it becomes not possible to effectively increase a surface area of the information storage plate.
Furthermore, in order to suppress the size difference "b" between between tie spacer film 12B and the first silicon film 11B (the base of the capacitor lower plate), the stopper film and the spacer film must be formed of a material having a small amount of etching subjected to in the photoresist removing step and the washing step. Accordingly, the degree of freedom in selection of material is limited.
For example, it is known that, a BPSG (borophosphosilicate glass) film can have a good reflow shape in a step portion as shown in FIG. 2, if a heat treatment is conducted at a temperature of not less than 800.degree. C. In FIG. 2, elements corresponding to those shown in FIGS. 1A to 1F are given the same Reference Numerals, and therefore, explanation thereof will be omitted. In the example shown in FIG. 2, the spacer film 12 is formed of BPSG. Accordingly, it is possible to prevent a residue of silicon which is apt to occur in the step at the time of etching back the second silicon film. If a good reflow shape cannot be obtained in the step in a region, such as a peripheral circuit region, other than a memory cell region, a residue 15C of silicon occurs as shown in FIG. 3, in which elements corresponding to those shown in FIG. 2 are given the same Reference Numerals, and therefore, explanation thereof will be omitted. As a result, when the spacer film is etch-removed by a hydrogen fluoride aqueous solution, the residue 15C of silicon, namely, a minute piece of silicon is peeled off. This is a cause of generation of so-called particles, which directly results in a lowered yield of production. Accordingly, use of the BPSG film as the spacer film may be considered to be effective in elevating the yield of production.
However, the BPSG film has a large amount of etching subjected to in the photoresist removing step and the washing step, and therefore, if the spacer film is formed of the BPSG film, the size difference "b" between the patterned spacer film and the patterned first silicon film is further increased. Because of this, it is difficult to use the RPSG film in the prior art.